15 research outputs found
Cryogenic Memory Technologies
The surging interest in quantum computing, space electronics, and
superconducting circuits has led to new developments in cryogenic data storage
technology. Quantum computers promise to far extend our processing capabilities
and may allow solving currently intractable computational challenges. Even with
the advent of the quantum computing era, ultra-fast and energy-efficient
classical computing systems are still in high demand. One of the classical
platforms that can achieve this dream combination is superconducting single
flux quantum (SFQ) electronics. A major roadblock towards implementing scalable
quantum computers and practical SFQ circuits is the lack of suitable and
compatible cryogenic memory that can operate at 4 Kelvin (or lower)
temperature. Cryogenic memory is also critically important in space-based
applications. A multitude of device technologies have already been explored to
find suitable candidates for cryogenic data storage. Here, we review the
existing and emerging variants of cryogenic memory technologies. To ensure an
organized discussion, we categorize the family of cryogenic memory platforms
into three types: superconducting, non-superconducting, and hybrid. We
scrutinize the challenges associated with these technologies and discuss their
future prospects.Comment: 21 pages, 6 figures, 1 tabl
CMOS-based Single-Cycle In-Memory XOR/XNOR
Big data applications are on the rise, and so is the number of data centers.
The ever-increasing massive data pool needs to be periodically backed up in a
secure environment. Moreover, a massive amount of securely backed-up data is
required for training binary convolutional neural networks for image
classification. XOR and XNOR operations are essential for large-scale data copy
verification, encryption, and classification algorithms. The disproportionate
speed of existing compute and memory units makes the von Neumann architecture
inefficient to perform these Boolean operations. Compute-in-memory (CiM) has
proved to be an optimum approach for such bulk computations. The existing
CiM-based XOR/XNOR techniques either require multiple cycles for computing or
add to the complexity of the fabrication process. Here, we propose a CMOS-based
hardware topology for single-cycle in-memory XOR/XNOR operations. Our design
provides at least 2 times improvement in the latency compared with other
existing CMOS-compatible solutions. We verify the proposed system through
circuit/system-level simulations and evaluate its robustness using a 5000-point
Monte Carlo variation analysis. This all-CMOS design paves the way for
practical implementation of CiM XOR/XNOR at scaled technology nodes.Comment: 12 pages, 6 figures, 1 tabl
Compact Model of a Topological Transistor
The precession of a ferromagnet leads to the injection of spin current and
heat into an adjacent non-magnetic material. Besides, spin-orbit entanglement
causes an additional charge current injection. Such a device has been recently
proposed where a quantum-spin hall insulator (QSHI) in proximity to a
ferromagnetic insulator (FI) and superconductor (SC) leads to the pumping of
charge, spin, and heat. Here we build a circuit-compatible Verilog-A-based
compact model for the QSHI-FI-SC device capable of generating two topologically
robust modes enabling the device operation. Our model also captures the
dependence on the ferromagnetic precision, drain voltage, and temperature with
an excellent (> 99%) accuracy
Cryogenic Neuromorphic Hardware
The revolution in artificial intelligence (AI) brings up an enormous storage
and data processing requirement. Large power consumption and hardware overhead
have become the main challenges for building next-generation AI hardware. To
mitigate this, Neuromorphic computing has drawn immense attention due to its
excellent capability for data processing with very low power consumption. While
relentless research has been underway for years to minimize the power
consumption in neuromorphic hardware, we are still a long way off from reaching
the energy efficiency of the human brain. Furthermore, design complexity and
process variation hinder the large-scale implementation of current neuromorphic
platforms. Recently, the concept of implementing neuromorphic computing systems
in cryogenic temperature has garnered intense interest thanks to their
excellent speed and power metric. Several cryogenic devices can be engineered
to work as neuromorphic primitives with ultra-low demand for power. Here we
comprehensively review the cryogenic neuromorphic hardware. We classify the
existing cryogenic neuromorphic hardware into several hierarchical categories
and sketch a comparative analysis based on key performance metrics. Our
analysis concisely describes the operation of the associated circuit topology
and outlines the advantages and challenges encountered by the state-of-the-art
technology platforms. Finally, we provide insights to circumvent these
challenges for the future progression of research
Superconducting Heater Cryotron-Based Reconfigurable Logic Towards Cryogenic IC Camouflaging
Superconducting electronics are among the most promising alternatives to
conventional CMOS technology thanks to the ultra-fast speed and ultra-high
energy efficiency of the superconducting devices. Having a cryogenic control
processor is also a crucial requirement for scaling the existing quantum
computers up to thousands of qubits. Despite showing outstanding speed and
energy efficiency, Josephson junction-based circuits suffer from several
challenges such as flux trapping leading to limited scalability, difficulty in
driving high impedances, and so on. Three-terminal cryotron devices have been
proposed to solve these issues which can drive high impedances (>100 k{\Omega})
and are free from any flux trapping issue. In this work, we develop a
reconfigurable logic circuit using a heater cryotron (hTron). In conventional
approaches, the number of devices to perform a logic operation typically
increases with the number of inputs. However, here, we demonstrate a single
hTron device-based logic circuit that can be reconfigured to perform 1-input
copy and NOT, 2-input AND and OR, and 3-input majority logic operations by
choosing suitable biasing conditions. Consequently, we can perform any
processing task with a much smaller number of devices. Also, since we can
perform different logic operations with the same circuit (same layout), we can
develop a camouflaged system where all the logic gates will have the same
layout. Therefore, this proposed circuit will ensure enhanced hardware security
against reverse engineering attacks.Comment: 12 pages, 5 figure
Machine Learning-powered Compact Modeling of Stochastic Electronic Devices using Mixture Density Networks
The relentless pursuit of miniaturization and performance enhancement in
electronic devices has led to a fundamental challenge in the field of circuit
design and simulation: how to accurately account for the inherent stochastic
nature of certain devices. While conventional deterministic models have served
as indispensable tools for circuit designers, they fall short when it comes to
capture the subtle yet critical variability exhibited by many electronic
components. In this paper, we present an innovative approach that transcends
the limitations of traditional modeling techniques by harnessing the power of
machine learning, specifically Mixture Density Networks (MDNs), to faithfully
represent and simulate the stochastic behavior of electronic devices. We
demonstrate our approach to model heater cryotrons, where the model is able to
capture the stochastic switching dynamics observed in the experiment. Our model
shows 0.82% mean absolute error for switching probability. This paper marks a
significant step forward in the quest for accurate and versatile compact
models, poised to drive innovation in the realm of electronic circuits
Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics
Phase transition materials (PTM) have garnered immense interest in concurrent postCMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (\u3c 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based selector. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers builtin tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a CockcroftWalton Multiplier, implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future